1. Technical Field
The present disclosure relates to providing a gray scale voltage and, more particularly to a gray scale voltage decoder and a digital-to-analog converter including a gray scale voltage decoder for a display device.
2. Discussion of Related Art
A display device converts digital image data to analog image data and displays the converted image data in a plurality of pixels of a display panel. Recently, almost all electronic devices such as a computer, a television or various mobile devices include such a display device. Various researches have been performed for reducing a size of a drive circuit in the display device generally implemented with an integrated circuit.
FIG. 1 is a block diagram illustrating a known display device.
Referring to FIG. 1, the display device includes a data driver 110, a scan driver 120 and a liquid crystal display (LCD) panel 130. The data driver 110 includes a digital-to-analog converter 111. The digital-to-analog converter 111 provides gray scale voltages corresponding to digital image data IDATA to pixels in the liquid crystal display panel 130. The digital-to-analog converter 111 may include a gray scale voltage decoder. The gray scale voltage decoder can receive gray scale voltages, select one of the gray scale voltages according to pixel data of the digital image data IDATA, and output the selected gray scale voltage. The gray scale voltage decoder occupies a relatively large space in the display device.
FIG. 2 is a block diagram illustrating a conventional gray scale voltage decoder of a display device. It is assumed that one pixel data correspond to six bits in FIG. 2.
The gray scale voltage decoder 200 selects one of sixty-four gray scale voltages according to six-bit digital image data, that is, one pixel data, to output the selected gray scale voltage. Referring to FIG. 2, the gray scale voltage decoder 200 of the display device may have a hierarchical structure for reducing the chip size. The gray scale voltage decoder 200 includes a first decoding unit 210 and a second decoding unit 220.
The first decoding unit 210 selects some of the gray scale voltages in response to the lower three bits DS1 of the digital image data and outputs the selected gray scale voltages. The first decoding unit 210 includes row blocks RW11 through RW88. Each of the row blocks receives one of the gray scale voltages V0 through V63 and outputs the received gray scale voltage in response to the lower three bits DS1 of the digital image data.
The second decoding unit 220 receives the gray scale voltages selected by the first decoding unit 210, selects one of the selected gray scale voltages in response to upper three bits DS2 of the digital image data and outputs the selected one gray scale voltage, which is an analog signal OUT.
FIG. 3 is a circuit diagram illustrating the gray scale voltage decoder 200 shown in FIG. 2 implemented with NMOS transistors.
Referring to FIG. 3, each of the row blocks RW11 through RW88 included in the gray scale voltage decoder 200 shown in FIG. 2 may be implemented with NMOS transistors. The NMOS transistors may be serially coupled in each of the row blocks of the first decoding unit 210. Each of the NMOS transistors receives, through a gate terminal, one bit of the digital image data D0, DOB, D1, D1B, D2, D2B, D3, D3B, D4, D4B, D5 and D5B representing the lower three bits DS1 of the digital image data.
FIG. 4 is a circuit diagram illustrating row blocks included in the first decoding block 210 implemented as an integrated circuit.
In the portion of the conventional gray scale voltage decoder shown in FIG. 4, adjacent row blocks RW11 and RW12 may operate in response to different bits of the digital image data. Thus, even when some row blocks are not affected by some bits of the digital image data, the input lines DL0 through DL5 need to pass through all the row blocks in order to provide some of the bits of the digital image data to the other row blocks located adjacently. Accordingly, dummy transistors MND are inserted between active transistors MNA that are actually performing the switching operations in response to the digital image signal. In forming the dummy transistors MND, source terminals and drain terminals of the dummy transistors MND are merged to form short circuits. The dummy transistors are inserted because an implementation of the integrated circuit without the dummy transistors needs more intervals, according to design rules, between the input lines DL0 through DL5 passing through the active transistors MNA1 through MNA6 and the empty space.
The dummy transistors, which do not perform switching operations, occupy a large circuit area.